/////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineer: Kyle D. Gilsdorf
//
// Create Date: 08:07:29 11/04/2011
// Design Name: 
// Module Name: seg_display
// Project Name: Lab #2
// Target Devices: 
// Tool versions: 
// Description: The 7-Segment LED Display module drives the 4 separate LED
// 7-Segment LED Display devices mounted on the FPGA Board.
//
// Dependencies:
// - my_clock
//
// Revision 0.01 - File Created
// Additional Comments:
// - I have provided the entire alphabet so that you can change this to display
//   other text as well.
/////////////////////////////////////////////////////////////////////////////////

module slowclock 
  /*************************************************************************
   * Input/Output Declarations and Parameters                              *
   *************************************************************************/
  (// Global Signals                  // -----------------------------------
   input  wire clk,                   // System Clock
   output wire clk_50MHz);            // 

   parameter MSB = 2;

  /***********************************************************
   * Signal Declaration                                      *
   ***********************************************************/   
   reg [MSB:0] count1 = 0;

  /***********************************************************
   * Combinational Logic                                     *
   ***********************************************************/
   assign clk_50MHz = count1[MSB];

  /***********************************************************
   * Synchronous Logic                                       *
   ***********************************************************/
   always@(posedge clk)
      count1 <= count1 + 1;
	  
  /***********************************************************
   * Module Instantiation                                    *
   ***********************************************************/	  
endmodule

module seg_display 
  /*************************************************************************
   * Input/Output Declarations and Parameters                              *
   *************************************************************************/
  (// Global Signals                  // -----------------------------------
   input wire         clk,            // System Clock
   input wire         reset_b,        // Push Button for System Reset.
   // 7-Segment LED Interface         // -----------------------------------
   input  wire          reg_read,     // Register Select Address is valid
   input  wire [01:00]  reg_addr,     // Register Select
   output wire [03:00]  reg_data,     // 4-Bit register Value of currently
                                      // address register (valid it read is
                                      // active)
   // 7-Segment LED Display Interface // -----------------------------------
   output wire         dp_dis,        // Period Display
   output reg  [03:00] dis_control,   // Select which of the 4x7-Segment LED 
	                                  // Displays to activate.
   output reg  [06:00] led_dis);      // Select which of the 7 LED's in the 
	                                  // 7-Segment LED Display

   ///////////////////////////
   // 7-Segment LED Display //
   //       aaaaaaaa        //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //       ggggggggg       //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //       ddddddddd       //
   ///////////////////////////
   //                   6543210
   //                   gfedcba
   parameter _0_  = 7'b1000000;
   parameter _1_  = 7'b1111001;
   parameter _2_  = 7'b0100100;
   parameter _3_  = 7'b0110000;
   parameter _4_  = 7'b0011001;
   parameter _5_  = 7'b0010010;
   parameter _6_  = 7'b0000011;
   parameter _7_  = 7'b1111000;
   parameter _8_  = 7'b0000000;
   parameter _9_  = 7'b0010000;
   parameter A     = 7'b0000100;
   parameter B     = 7'b0000011;
   parameter C     = 7'b1000110;
   parameter D     = 7'b0100001;
   parameter E     = 7'b0000110;
   parameter F     = 7'b0001110;
   parameter G     = 7'b0010000;
   parameter H     = 7'b0001011;
   parameter I     = 7'b1001111;
   parameter J     = 7'b1100001;
   parameter K     = 7'b0001001;
   parameter L     = 7'b1000111;
   parameter M     = 7'b1101010;
   parameter N     = 7'b0101011;
   parameter O     = 7'b1000000;
   parameter P     = 7'b0001100;
   parameter Q     = 7'b0011000;
   parameter R     = 7'b0101111;
   parameter S     = 7'b0010010;
   parameter T     = 7'b0000111;
   parameter U     = 7'b1000001;
   parameter V     = 7'b1100011;
   parameter W     = 7'b1010101;
   parameter X     = 7'b0001001;
   parameter Y     = 7'b0010001;
   parameter Z     = 7'b0100100;
   parameter empty = 7'b1111111;

  /***********************************************************
   * Signal Declaration                                      *
   ***********************************************************/
   wire        clk_50MHz;
   reg [01:00] count;
	reg [27:00] delay_c;
	reg delay_flag;
	wire data_displayed;

  /***********************************************************
   * Combinational Logic                                     *
   ***********************************************************/
   assign dp_dis = 1'b1; // Disable to dot.

  /***********************************************************
   * Synchronous Logic                                       *
   ***********************************************************/
   always @(posedge clk_50MHz, negedge reset_b)
      if (~reset_b) begin
         count <= 2'd0;
         led_dis <= empty;
         dis_control <= 4'b1111;
			delay_c <= 28'd0;
      end
      else begin
         count  <= count + 1;
			delay_c <= delay_c +1;
         case (count) 
            0 : begin
				dis_control <= 4'b1110;
				led_dis <= _0_;
				if (delay_c == 100000000) 
					begin
					delay_flag = 1'b1;
					PED p1( .i_signal(delay_flag), .i_clk(clk_50MHz), .i_rst_b(reset_b), .o_pulse(data_displayed));
					end
				end
				
            1 : begin
				dis_control <= 4'b1101;
				led_dis <= _0_;
				if (delay_c == 100000000) 
					begin
					delay_flag = 1'b1;
					PED p1( .i_signal(delay_flag), .i_clk(clk_50MHz), .i_rst_b(reset_b), .o_pulse(data_displayed));
					end
			end
            2 : begin
				dis_control <= 4'b1011;
				led_dis <= _2_; //CHANGE THIS
				if (delay_c == 100000000) 
					begin
					delay_flag = 1'b1;
					PED p1( .i_signal(delay_flag), .i_clk(clk_50MHz), .i_rst_b(reset_b), .o_pulse(data_displayed));
					end
			end
            3 : begin
				dis_control <= 4'b0111;
				led_dis <= _3_; //CHANGE THIS
				count <= 2'd0;
				if (delay_c == 100000000) 
					begin
					delay_flag = 1'b1;
					PED p1( .i_signal(delay_flag), .i_clk(clk_50MHz), .i_rst_b(reset_b), .o_pulse(data_displayed));
					end
			end
         endcase
      end

  /***********************************************************
   * Module Instantiation                                    *
   ***********************************************************/
   slowclock
      my_clock (
         .clk       (clk),        // I      50MHz
         .clk_50MHz (clk_50MHz)); // I      800Hz

endmodule
